Logic circuits

ABSTRACT

A novel type of logic circuit, the output binary logic functions or signals thereof being defined according to whether each of the output voltage differences is positive or negative, is so organized that the logic circuit comprises a plurality of current switches to each of which is applied an input signal composed of a pair of voltages, and a binary output of 0 and 1 is delivered therefrom, at most two circuit elements wherein the binary outputs from said plurality of current switches are added in a linear manner, a plurality of circuit positions the potentials of which are in a linear relation to the resultant voltage obtained in said circuit elements, and means for producing voltage differences between said plurality of circuit positions, whereby a plurality of said binary logic functions or signals are simultaneously obtained. In another aspect, a plurality of reference potentials may also be provided, and the voltage differences between any of said plurality of circuit positions and said plurality of reference potentials may be employed as the outputs of the logic circuit.

United States Patent Mori et al.

[is] 3,681,616 [451 Aug. 1, 1972 LOGIC CIRCUITS [72] Inventors: Ryoichi Mori; Hiroaki Tajima; Yoshio Tsuji; Noriaki Sanechlka, all of Tokyo-to, Japan [73] Assignee: Kogyo Gflutsuin, Tokyo-to, Japan [22] Filed: Oct. 31, 1969 [21] Appl. No.: 872,824

[58] Field of Search ..307/203, 207, 215, 218; 330/30 D [56] References Cited UNITED STATES PATENTS 3,475,622 10/1969 Andersen et al ..330/30 3,446,989 5/1969 Allen et al. ..307/215 3,508,076 4/1970 Winder ..330/30 Primary Examiner-John S. Heyman Assistant Examiner-B. P. Davis Atrorney-Holman 8L Stern S 7 ABSTRACT A novel type of logic circuit, the output binary logic functions or signals thereof being defined according to whether each of the output voltage differences is positive or negative, is so organized that the logic circuit comprises a plurality of current switches to each of which is applied an input signal composed of a pair of voltages, and a binary output of 0 and l is delivered therefrom, at most two circuit elements wherein the binary outputs from said plurality of current switches are added in a linear manner, a plurality of circuit positions the potentials of which are in a linear relation to the resultant voltage obtained in said circuit elements, and means for producing voltage differences between said plurality of circuit positions, whereby a plurality of said binary logic functions or signals are simultaneously obtained. In another aspect, a plurality of reference potentials may also be provided, and the voltage differences between any of said plurality of circuit positions and said plurality of reference potentials may be employed as the outputs of the logic circurt.

1 Claim, 36 Drawing Figures Ero En Ern PATENTEUMI I I912 3.681.616

saw 01 HF 21 PATENTEDM 1 m2 3.681.616

SHEET 03 0F 21 FIG. 5 j

PATENTED 1 I973 3.681.616

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Y0 VLFEIOM PATENTED 1 I973 3.681. 616

saw 05 DF 21 PATENTEU 1 I972 3.681.616

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sum 01 or 21 PATENTEU H97? 3581,6316

sum 08 HF 21 PATENTEDAus H972 3.681.616

sum 10 UP 21 FIG. 22

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FlG.24(b) FIG.24(C) PATENTEBw Hm 3.681.616

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sum 15 HF 21 F|G.26(0) FlG.26(b) FIG. 26(6) h DATA PATENTED 1 1973 3,681,616

UNITS EMPLOYED FOR ALL vALuEs IN was TABLE ARE VOLTS.

TABLE 2, WHERElNmISAN EVEN NUMBER. n=%+ AND L=O,

PA TENTED M19 1 i973 sum 19 HF 21 FIG. 34

UNITS EMPLOYED FOR ALL VALUES IN THIS TABLE ARE VOLTS.

TABLE 3. WHEREIN TW AN EVEN NUMBER. n=LAND 

1. A basic logic circuit for delivering logically two valued and physically multi-valued signals defined according to whether each of the output voltage differences thereof is positive or negative, comprising a plurality of current switches, each of which has at least two input terminals, and said basic logic circuit having at most two load resistors wherein output currents from said plurality of current switches are linearly added in a desired range, and at least one circuit positions having either one of a potential linearly related to an added output in either of said at most two load resistors whereby a plurality of logic signals and negations thereof as defined are delivered simultaneously, wherein each of said plurality of current switches consists of two portions each having an input, whereby a plurality of ''''median'''' functions consisting of from M1 to Mm and from M1 to Mm are obtained by said plurality of current switches and said at most two linearly adding load resistors, where a median function Mj (x1, x2, . . . , xm) of m binary variables is defined as follows: 